The present disclosure generally relates to semiconductor devices, and particularly to field effect transistors including an embedded source/drain region having an n-doped silicon liner and an n-doped silicon-carbon alloy interior portion, and methods of manufacturing the same.
Carbon has a smaller atomic radius than silicon. As a consequence, a silicon-carbon alloy in which the atomic concentration of carbon does not exceed 2.5%, which is the solid state solubility limit for C in Si, can be grown epitaxially on a silicon surface. A silicon-carbon alloy has a smaller lattice constant than single crystalline silicon, and as such, a silicon-carbon alloy epitaxially grown and embedded in a trench within a single crystalline silicon substrate applies tensile stress to the surrounding regions. This property is advantageously employed to form n-type transistors having embedded n-doped silicon-carbon alloy source/drain regions so that a tensile stress applied to an n-type transistor enhances the mobility of minority charge carriers, i.e., mobility of electrons.
In order to prevent formation of an n-doped silicon-carbon alloy on undesirable locations, the deposition of embedded source/drain regions is performed by selective epitaxy. During selective epitaxy, a reactant gas and an etchant gas are flowed into a process chamber simultaneously or alternately in order to provide growth of a silicon-carbon alloy on crystalline silicon surfaces, while preventing continued deposition of a silicon-carbon alloy on dielectric surfaces. In some cases, the etchant gas can be formed as a natural byproduct of the reactant gas. For example, dichlorosilane (SiH2Cl2), which is a reactant for depositing silicon, generates hydrogen chloride (HCl) gas as a natural byproduct during the reaction, and thus, flowing dichlorosilane alone can achieve the effect of selective epitaxy because the byproduct HCl can function as an etchant for a selective epitaxy process. Additional HCl may also be provided, if desired, with dichlorosilane.
Experimentally, attempts to use an n-doped silicon-carbon alloy for embedded source/drain regions encounters a practical problem of cavity formation at an interface between preexisting source/drain extension regions and epitaxially grown N-type Silicon-Carbon. In prior art structures, deposition of the doped silicon-carbon alloy is limited by the supply of reactant gases into a geometry having a high aspect ratio at the interfaces between source/drain extension regions and the dielectric gate spacers. However, etching of the doped silicon material of the source/drain extension regions is not limited as much by the supply of etchant gases. Thus, the ratio between the deposition rate and the etch rate near the interface between the source/drain extension regions and the dielectric gate spacers is significantly lower than the ratio the deposition rate and the etch rate at locations farther away from the interface between the source/drain extension regions and the dielectric spacers. This local imbalance between the deposition rate and the etch rate induces formation of cavities during attempted selective epitaxy processes for depositing a silicon-carbon alloy. Further, the deposition of embedded doped silicon-carbon alloy portions proceeds anisotropically depending on the orientation of crystallographic surfaces of the underlying silicon surface. Thus, once the cavities are formed, deposition of a carbon-doped silicon material proceeds slowly along some orientations, preventing filling of the cavities, and thereby perpetuating the presence of the cavities. These cavities penalize the link-up resistance between extension and epitaxial source/drain regions causing a undesired resistance increase in the transistor.
Referring to FIG. 1, a prior art exemplary structure illustrates the formation of a cavity 133 at a junction among a preexisting semiconductor material, a dielectric material portion, and an epitaxially deposited phosphorus-doped silicon-carbon alloy. Specifically, the prior art exemplary structure includes a buried insulator layer 106, a p-doped single crystalline silicon layer 110, a source/drain extension region 132 including an n-doped single crystalline silicon material, and a dielectric material layer 150. A trench is formed in the p-doped single crystalline silicon layer 110 employing the dielectric material layer 150 as an etch mask so that a vertical sidewall of the source/drain extension region 132 is exposed. The vertical sidewall of the source/drain extension region 132 is typically vertically coincident with the sidewall of the dielectric material layer 150. A sidewall and a top surface of the p-doped single crystalline silicon layer 110 are also exposed at a lower portion of the trench. A phosphorous-doped silicon-carbon alloy portion 138 is deposited on the exposed semiconductor surfaces by selective epitaxy. The selective epitaxy process introduces some etching of the exposed semiconductor material. The etching is more prominent directly underneath the dielectric material layer 150 as discussed above, thereby producing a cavity 133 at the junction of the source/drain extension region 132 the dielectric material layer 150, and the phosphorous-doped silicon-carbon alloy portion 138. The lateral and vertical dimensions of the cavity 133 can be on the order of 30 nm. Typically, the cavity 133 is not filled even after deposition of a contact-level dielectric material layer 180, which typically includes silicon oxide.
Such cavities, when formed at an interface between a source/drain extension region and an embedded doped silicon-carbon alloy portion, have a deleterious effect on the performance of the field effect transistors because the resistance between an embedded doped silicon-carbon alloy portion, which function as a source/drain region, and the source/drain extension regions adjacent to the embedded doped silicon-carbon alloy portion increase with the size of the cavities. In order to provide a high performance transistor, the contact resistance between source/drain extension regions and embedded source/drain regions needs to be reduced.